Question & Answer
Question
Why do I get a system completion code 0C4 (S0C4) in DFHSIP at offset 70584 and interruption code 003B when I start CICS after an upgrade to CICS Transaction Server for z/OS (CICS TS) V5.2? I am using CA ENF and CA Top Secret from CA Technologies.
I receive the following messages then CICS hangs:
+DFHSI1500 *applid* CICS startup is in progress for CICS Transaction Server Version 5.2.0
IEA995I SYMPTOM DUMP OUTPUT
139
SYSTEM COMPLETION CODE=0C4 REASON CODE=0000003B
TIME=15.10.30 SEQ=02701 CPU=0000 ASID=0073
PSW AT TIME OF ERROR 078D1001 94070584 ILC 6 INTC 3B
ACTIVE LOAD MODULE ADDRESS=14000000 OFFSET=00070584
NAME=DFHSIP
Answer
DFHSIP is a large load module that includes many CICS internal programs. In this case, the PSW was pointing at DFHKESTX +x'1CCC' at PTF level UI25653.
To determine if your problem is the same, you can use IPCS command SUMM FORMAT REGS to view the RTM2WA SUMMARY (reorganized to show it better here) in a system dump:
-----------------------------------------------------------------------
.
RTM2WA SUMMARY
+001C COMPLETION CODE 840C4000
+06D0 BEA...... 00000000 14070548
+06D8 PSW AT TIME OF ERROR: 07851001 80000000 00000000 14070584
+06C8 TRANSLATION EXCEPTION IDENTIFICATION: 00000000 94283000
+06C8 TRANSLATION EXCEPTION IDENTIFICATION: 00000000 94283000
+0084 INSTRUCTION LENGTH CODE: D006 INTERRUPTION CODE: 003B
.
64-BIT GPRS FROM THE RB/XSB
0-1 00000000_94283000 00000000_942838E8
2-3 00000000_14223B60 00000000_14071688
4-5 00000000_142442D8 00000000_14244200
6-7 00000000_14244200 00000000_14244200
8-9 00000000_1421B680 D006003B_7FFFFBD0
10-11 00000000_40404040 00000000_1421B680
12-13 00000000_46418BF8 00000000_14223B60
14-15 00000000_14223B60 00000000_7F569A18
-----------------------------------------------------------------------
The RTM2WA SUMMARY contains the full PSW which is in 64bit mode (...1 8...). The interrupt code is 3B, which is a Translation Exception because a referenced address is outside the region.
The PSW points into DFHKESTX at +x'1CCC' PTF level UI25653. The instruction referenced a register that contained an address. That address had the x'80' bit on in the first byte. If the PSW were in 31bit mode, the x'80' bit would be ignored. But, because the PSW is in 64bit mode, the x'80' bit is taken as part of the address.
The problem happened because DFHKESTX is CICS' ESTAE exit. It was trying to process a previous error and needed to go to module DFHLDLD. But DFHLDLD had been replaced by a vendor product, CA ENF that worked with security product CA Top Secret.
CA ENF did not handle the 64bit switch correctly because CA ENF maintenance that adds support for CICS TS 5.2 is missing. Applying the CA Common Services maintenance should resolve the problem. Contact the vendor CA Technologies for the fixes.
Product Synonym
CICS/TS CICSTS CICS TS CICS Transaction Server
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Document Information
Modified date:
11 March 2016
UID
dwa1256279